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USBULC6-2M6
Ultra large bandwidth ESD protection
Features

2 data line 15 kV ESD protection Protects 5 V VBUS when applicable Ultra low capacitance: 0.65 pF at F = 240 MHz Very low leakage current: 0.5 A max. Fast response time compared with varistors QFN 6 lead package RoHS compliant Figure 1.
QFN (pin view)
Benefits
Functional diagram (top view)
ESD protection of VBUS (when applicable) High bandwidth to minimize impact on data signal quality

Low PCB space occupation Low leakage current profides longer operation of battery powered devices Higher reliability offered by monolithic integration
Complies with these standards:
IEC 61000-4-2 level 4 - 15 kV air discharge - 8 kV contact discharge
Description
The USBULC6-2M6 is a monolithic, application specific discrete device dedicated to ESD protection of high speed interfaces. Its ultra low line capacitance provides high bandwidth and secures a high level of signal integrity without compromizing the protection of downstream sensitive chips against the most stringent characterized ESD strikes.
Applications
USB 2.0 ports including Hi-Speed USB ports up to 480 Mb/s as well as full and low speed USB ports Ethernet port: 10/100/1000 Mb/s Video line protection Portable electronics

November 2007
Rev 1
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www.st.com
Characteristics
USBULC6-2M6
1
Characteristics
Table 1.
Symbol VPP Tstg Tj TL Peak pulse voltage Storage temperature range Maximum junction temperature Lead solder temperature (10 seconds duration)
Absolute ratings
Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883G-Method 3015-7 Value 15 15 25 -55 to +150 150 260 Unit kV C C C
Table 2.
Symbol IRM VBR
Electrical characteristics (Tamb = 25 C)
Value Parameter Leakage current Breakdown voltage between VBUS and GND Test conditions Min. VRM = 5 V IR = 1 mA IPP = 1 A, tp = 8/20 s Any I/O pin to GND 6 12 17 0.95 0.65 0.020 0.5 0.35 0.55 0.4 1.1 0.85 pF Typ. Max 0.5 A V V V Unit
VCL
Clamping voltage IPP = 5 A, tp = 8/20 s Any I/O pin to GND VR = 0 V, F = 1 MHz Any I/O pin to ground
Ci/o-GND
Capacitance between I/O and GND VR = 0 V, F = 240 MHz Any I/O pin to ground Capacitance variation between I/O and GND VR = 0 V, F = 1 MHz Any I/O pin to ground VR = 0 V, F = 1 MHz Ground not connected
Ci/o-GND
Ci/o-i/o
Capacitance between I/O VR = 0 V, F = 240 MHz Ground not connected
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USBULC6-2M6
Characteristics
Figure 2.
Line capacitance versus frequency Figure 3. (typical values)
Relative variation of leakage current versus junction temperature (typical values)
C(fF)
1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 0 1 2 3 F(GHz)
IRM[Tj] / IRM[Tj=25C]
5 4
I/O - GND
3
2
I/O - I/O
Tj(C)
1 25 50 75 100 125
Figure 4.
0.00
Attenuation measurement
Figure 5.
dB
0.00
Crosstalk measurements
S21(db)
- 4.00
- 30.00
- 8.00
- 60.00
- 12.00
- 90.00
F(Hz)
- 16.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
F (Hz)
- 120.00 300.0k 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G
Figure 6.
Remaing voltage on I/O1 after the USBULC6-2M6 during positive ESD surge (15 kV Air)
Figure 7.
Remaing voltage on I/O2 after the USBULC6-2M6 during negative ESD surge (15 kV Air)
10V/Div
10V/Div
100ns/Div
100ns/Div
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Characteristics
USBULC6-2M6
Figure 8.
Remaing voltage on VBUS after the USBULC6-2M6 during positive ESD surge (15 kV Air)
Figure 9.
Remaing voltage on VBUS after the USBULC6-2M6 during negative ESD surge (15 kV Air)
10V/Div
10V/Div
100ns/Div
100ns/Div
Figure 10. Eye diagram PCB only 400 mV amplitude, F = 480 Mbps
Figure 11. Eye diagram PCB + USBULC6-2M6 400 mV amplitude, F = 480 Mbps
Horiz: 350 ps/div Vert: 100 mV/div
Horiz: 350 ps/div Vert: 100 mV/div
Figure 12. Eye diagram PCB + USBULC6-2M6, +5 V on VBUS decoupling capacitor 100 nF, 400 mV amplitude, F = 480 Mbps
Horiz: 350 ps/div Vert: 100 mV/div
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USBULC6-2M6
Application example
2
Application example
Figure 13. One differential line
D+
I/O1 1 2 3 6 5 4 I/O1
To GND plane
I/O2
100 nF I/O2
D-
3
Ordering information scheme
Figure 14. Ordering information scheme
USB ULC 6 - 2 M6
Product Designation Ultra low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 2 = 2 lines Package QFN - 6 leads
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Package information
USBULC6-2M6
4
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free. The category of second level Interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Table 3. Micro QFN 1.45x1.00 6L dimensions
Dimensions
D
N
Ref.
E
Millimeters Min. Typ. 0.55 0.02 0.25 1.45 1.00 0.50 0.20 0.30 0.35 0.40 0.008 Max. 0.60 0.05 0.30 Min.
Inches Typ. Max.
1
2
A A1
0.50 0.00 0.18
0.020 0.022 0.024 0.000 0.001 0.002 0.007 0.010 0.012 0.057 0.039 0.020
A A1
1 2
b D(1)
L k b e
E(1) e
(2)
K L
0.012 0.014 0.016
1. 0.1 mm 2. 0.05 mm
Note:
Product marking may be rotated by 90 for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Figure 15. Footprint dimensions in mm [inches]
0.50 [0.020] 0.25 [0.010]
0.65 [0.026] 0.30 1.60 [0.012] [0.063]
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Recommendation on PCB assembly
5
5.1
Recommendation on PCB assembly
Stencil opening design
1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness)
Figure 16. Stencil opening dimensions.
L
T
W
b)
General Design Rule Stencil thickness (T) = 75 ~ 125 m W Aspect Ratio = ---- 1.5 T LxW Aspect Area = --------------------------- 0.66 2T ( L + W )
2.
Reference design a) b) Stencil opening thickness: 100 m Stencil opening for leads: Opening to footprint ratio is 90%.
5.2
Solder paste
1. 2. 3. 4. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. "No clean" solder paste is recommended. Offers a high tack force to resist component movement during high speed Solder paste with fine particles: powder particle size is 20-45 m.
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Recommendation on PCB assembly
USBULC6-2M6
5.3
Placement
1. 2. 3. 4. Manual positioning is not recommended. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering Standard tolerance of 0.05 mm is recommended. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
5. 6.
5.4
PCB design preference
1. 2. To control the solder paste amount, the closed via is recommended instead of open vias. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
5.5
Reflow profile
Figure 17. ST ECOPACK(R) recommended soldering reflow profile for PCB mounting
Temperature (C)
260C max 255C 220C 180C 125 C
2C/s recommended 2C/s recommended 6C/s max 6C/s max
3C/s max 3C/s max
0 0 1 2 3 4 5
10-30 sec 90 to 150 sec 90 sec max
6
7
Time (min)
Note:
Minimize air convection currents in the reflow oven to avoid component movement.
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USBULC6-2M6
Ordering information
6
Ordering information
Table 4. Ordering information
Marking T(1) Package QFN Weight 2.2 mg Base qty 3000 Delivery mode Tape and reel
Order code USBULC6-2M6
1. The marking can be rotated by 90 to diferentiate assembly location
7
Revision history
Table 5.
Date 29-Nov-2007
Document revision history
Revision 1 First issue Description of changes
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USBULC6-2M6
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